INNOVENTIONS ACTIVITIES IN THE ACADEMIA

This page outlines Dr. David Y. Feinstein's work in the academia. Here is a list of recent publications.

### Academic Publications by David Y. Feinstein

- "Modeling System Threat Probabilities Using Mixed-Radix Multiple-Valued Logic Decision Diagrams", Journal of Multiple-Valued Logic and Soft Computing, (to appear, with T.W. Manikas and M.A. Thornton).
- "Quantum Multiple-Valued Decision Diagram: The Case of Skipped Variables", Journal of Multiple-Valued Logic and Soft Computing, vol. 24, 2015, no. 1-4, pp. 93-108, ( with M.A. Thornton).
- "Using the Asynchronous Paradigm for Reversible Sequential Circuit Implementation", IEEE International Symposium on Multiple Valued Logic (ISMVL), May 14-16, 2012, pp. 305-310, (with M.A. Thronton).
- "Modeling Medical System Threats with Conditional Probabilities using Multiple-valued Logic Decision Diagrams", IEEE International Symposium on Multiple Valued Logic (ISMVL), May 14-16, 2012, pp. 244-249, (with T.W. Manikas and M.A. Thronton).
- "Reversible Logic Synthesis Based on Decision Diagram Variable Ordering", Journal of Multiple-Valued Logic and Soft Computing, vol. 19, no. 4, 2012, pp. 325-340 (with M.A. Thornton).
- "On the Skipped Variables of Quantum Multiple-valued Decision Diagrams", IEEE International Symposium on Multiple Valued Logic (ISMVL), May 23-25, 2011, pp. 164-168, (with M.A. Thornoton).
- "Using Multiple-Valued Logic Decision Diagrams to Model System Threat Probabilities", IEEE International Symposium on Multiple Valued Logic (ISMVL), May 23-25, 2011, pp. 263-267, (with T. W. Manikas and M.A. Thornoton).
- "Minimization of Quantum Multiple-Valued Decision Diagrams using Data Structure Metrics", Journal of Multiple-Valued Logic and Soft Computing, vol. 15, no. 4, pp. 361-377, (with M.A. Thornton and D.M. Miller).
- "On the Guidance of Reversible Logic Synthesis by Dynamic Variable Ordering", IEEE International Symposium on Multiple Valued Logic (ISMVL), May 21-23, 2009, pp. 132-138, (with M.A. Thronton).
- "QMDD Minimization using Sifting for Variable Reordering, Journal of Multiple-Valued Logic and Soft Computing", vol. 13, no. 4-6, 2007, pp. 537-552, (with M.A. Thronton and D.M. Miller).
- "On the Data Structure Metrics of Quantum Multiple-Valued Decision Diagrams", IEEE International Symposium on Multiple Valued Logic (ISMVL), May 22-23, 2008, pp. 138-143, (with M.A. Thronton and D.M. Miller).
- "Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits", Proceedings of the IEEE/ACM Design, Automation and Test in Europe (DATE), March 10-14, 2008, pp. 1378-1381, (with M.A. Thronton and D.M. Miller).
- "Variable Reordering and Sifting for QMDD", IEEE International Symposium on Multiple Valued Logic (ISMVL), May 14-16, 2007, electronic proceedings, Session 2B, paper 1, (with M.A. Thronton and D.M. Miller).
- "System-on-Chip Power Consumption Refinement and Analysis", Proceedings of the IEEE Dallas Workshop on Circuits and Systems, November 15-16, 2007, pp. 81-84, (with M.A. Thronton and F. Kocan).
- "Quantum Logic Circuit Simulation Based on the QMDD Data Structure", Proceedings of the Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RMW), May 16, 2007, pp. 99-105, (with D. Goodman, M.A. Thronton and D.M. Miller).
- "ESOP Transformation to Majority Gates for Quantum-dot Cellular Automata Logic Synthesis", Proceedings of the Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RMW), May 16, 2007, pp. 43-50, (with M.A. Thronton).
- "Prefix Parallel Adder Virtual Implementation in Reversible Logic", IEEE Region 5 Technical Conference, April 20-22, 2007, pp. 74-80, (with M.A. Thronton and V.S.S. Nair).
- " Advances in Quantum Computing Fault Tolerance and Testing", IEEE High Assurance Systems Engineering Symposium, November 14-16, 2007, (with M.A. Thronton and V.S.S. Nair).
- "A View-Navigation System for Hand-Held Portable Displays", Information Display, Vol. 19, No. 7, pp. 22-25, July 2003.

Here is an abstract of Dr. Feinstein's Ph.D. dissertation (Southern Methodist University, Dallas, Texas).

### David Y. Feinstein's DISSERTATION: COMPUTER-AIDED-DESIGN METHODS FOR EMERGING QUANTUM COMPUTING TECHNOLOGIES

Emerging quantum computing technologies are poised to replace standard CMOS logic when
the exponential size reduction reaches sub-atomic dimensions. Quantum circuits
are reversible and therefore promise the potential of computation without
energy loss. This research considers computer aided design (CAD) methods for
all major aspects of quantum computing circuit design including logic
synthesis, simulation, verification, and testing.

The technologies we investigate include quantum cell automata (QCA) and general
quantum circuits (QC), with significantly more emphasis on the later. The
recently introduced quantum multi-valued decision diagram (QMDD) provides an
efficient method to represent and simulate quantum (and other classical
reversible) circuits. A major contribution of this dissertation is the
development of a sift-like minimization as well as structure metrics based
minimization techniques for QMDD. We have used the enhanced QMDD to efficiently
simulate quantum circuits as well as quantum vectors.

Our early investigation of reversible logic is concerned with a virtual implementation
that uses a direct translation of relatively complex binary functions into
circuits composed of Fredkin reversible gates. This allowed us to project size
and speed complexity of complex reversible circuits, although this direct
translation approach fails to minimize garbage inputs and outputs. To achieve
proper garbage minimization, one must synthesize reversible logic using gate
cascades with appropriate optimization methods embedded that attempt to
minimize the total number of lines in the circuit. To that end, we developed a
novel QMDD-based tool for cascade logic synthesis that utilizes the QMDD
minimized variable order for lexicographical synthesis with garbage
minimization included as an optimization criterion.

We developed a synthesis tool that investigates the QCA native 3-input majority
gates ability to implement complex logic circuits. In particular, we explore
the benefit of transforming the logic description into exclusive sum of
products (ESOP) forms prior to implementation in the majority gates.

We survey recent efforts in establishing the
foundation for QC testing and fault tolerant QC. We project the potential use
of random tests as well as built in self test (BIST) techniques for future QC.
A major contribution of this dissertation is the investigation of partially
redundant reversible logic. Detection of partially redundant logic within any
design, reversible or irreversible, has ramifications for logic synthesis, for
design verification, and for design for test (DFT) issues.

**David's dissertation may be accessed
here** (PDF file). David's Doctoral
Advisor and collaborator was
**Prof. Mitchell A.
Thornton
**